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IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort? Static RAM
Address Counter Control Operations
Each port on the IDT70V5388/78 is equipped with
an internal address counter, to ease the process of
bursting data into or out of the device. Truth Table II depicts
the specific operation of the counter functions, to include
the order of priority among the signals. All counter controls
are independent of chip enables. The device supports the
ability to load a new address value on each access, or to
load an address value on a given clock cycle via the CNTLD
control and then allow the counter to increase that value by
preset increments on each successive clock via the
CNTINC control (see also the Counter Mask Operations
section that follows). The counter can be suspended on
any clock cycle by disabling the CNTINC , and it can be
reset to zero on any clock cycle by asserting the CNTRST
control. CNTRST only affects the address value stored in the
counter: it has no effect on the counter mask register.
When the counter reaches the maximum value in
Industrial and Commercial Temperature Ranges
the array (i.e., address FFFFh for IDT70V5388 and address
7FFFh for IDT70V5378) or it reaches the highest value
permitted by the Counter Mask Register, it then ‘wraps
around’ to the beginning of the array. When Address Min is
reached via counter increment (i.e., not as a result of an
external address load), then the CNTINT signal for that port
is driven low for one clock cycle, automatically resetting on
the next cycle.
When the CNTRD control is asserted, the
IDT70V5388/78 will output the current address stored in the
internal counter for that port as noted in the Load and Read
Address Counter timing waveform on page 19. The address
will be output on the address lines. During this output, the
data I/Os will be driven in accordance with the settings of
the chip enables, byte enables, and the output enable on
that port: the device does not automatically tri-state these
pins during the address readback operation.
CNTRD
MKRD
Read Back
Register
Addr.
Read
Back
Address
MKLD
Mask
Register
Memory
Array
(I/O)
Counter/
CNTLD
CNTINC
CNTRST
CLK
Address
Register
Figure 4. Logic Block Diagram for Read Back Operations
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